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author | baude <bbaude@redhat.com> | 2018-06-20 13:23:24 -0500 |
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committer | Atomic Bot <atomic-devel@projectatomic.io> | 2018-06-29 20:44:09 +0000 |
commit | b96be3af1b9d00662758211420c955becbaf2f9e (patch) | |
tree | d5cd7760de51bee819173a86317e1decbe0aa620 /vendor/golang.org/x/sys/cpu/cpu.go | |
parent | 8d114ea4d81df474137b73a656012716500a2242 (diff) | |
download | podman-b96be3af1b9d00662758211420c955becbaf2f9e.tar.gz podman-b96be3af1b9d00662758211420c955becbaf2f9e.tar.bz2 podman-b96be3af1b9d00662758211420c955becbaf2f9e.zip |
changes to allow for darwin compilation
Signed-off-by: baude <bbaude@redhat.com>
Closes: #1015
Approved by: baude
Diffstat (limited to 'vendor/golang.org/x/sys/cpu/cpu.go')
-rw-r--r-- | vendor/golang.org/x/sys/cpu/cpu.go | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/vendor/golang.org/x/sys/cpu/cpu.go b/vendor/golang.org/x/sys/cpu/cpu.go new file mode 100644 index 000000000..3d88f8667 --- /dev/null +++ b/vendor/golang.org/x/sys/cpu/cpu.go @@ -0,0 +1,38 @@ +// Copyright 2018 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Package cpu implements processor feature detection for +// various CPU architectures. +package cpu + +// CacheLinePad is used to pad structs to avoid false sharing. +type CacheLinePad struct{ _ [cacheLineSize]byte } + +// X86 contains the supported CPU features of the +// current X86/AMD64 platform. If the current platform +// is not X86/AMD64 then all feature flags are false. +// +// X86 is padded to avoid false sharing. Further the HasAVX +// and HasAVX2 are only set if the OS supports XMM and YMM +// registers in addition to the CPUID feature bit being set. +var X86 struct { + _ CacheLinePad + HasAES bool // AES hardware implementation (AES NI) + HasADX bool // Multi-precision add-carry instruction extensions + HasAVX bool // Advanced vector extension + HasAVX2 bool // Advanced vector extension 2 + HasBMI1 bool // Bit manipulation instruction set 1 + HasBMI2 bool // Bit manipulation instruction set 2 + HasERMS bool // Enhanced REP for MOVSB and STOSB + HasFMA bool // Fused-multiply-add instructions + HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers. + HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM + HasPOPCNT bool // Hamming weight instruction POPCNT. + HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64) + HasSSE3 bool // Streaming SIMD extension 3 + HasSSSE3 bool // Supplemental streaming SIMD extension 3 + HasSSE41 bool // Streaming SIMD extension 4 and 4.1 + HasSSE42 bool // Streaming SIMD extension 4 and 4.2 + _ CacheLinePad +} |